1. Field of the Invention
The present invention relates generally to dynamic semiconductor memory devices. More particularly, the present invention relates to dynamic semiconductor memory devices comprising memory cell arrays including a plurality of word lines, a plurality of bit lines and a plurality of memory cells connected to intersections of the word lines and the bit lines, the plurality of bit lines including bit line pairs each including a bit line for reading/writing information of a memory cell and a bit line for providing a reference potential, and further including sense amplifiers each connected to each bit line pair for detecting and amplifying a potential difference between the bit lines.
2. Description of the Background Art
FIG. 4 is a block diagram showing an arrangement of a major part of a conventional dynamic random access memory (referred to as DRAM hereinafter). Referring to FIG. 4, a plurality of bit line pairs BL0 and BL0, and BL1 and BL1 are arranged so as to intersect a plurality of word lines WL0 and WL1. Memory cells MC are connected at intersections between respective bit line pairs BL0 and BL0, and BL1 and BL1 and the word lines WL0 and WL1. Each memory cell MC includes a transfer gate TG comprising an N channel MOS transistor, and a capacitance Cs for storing information of a "H" (high) level or a "L" (low) level. Dummy word lines DWL0 and DWL1 are arranged so as to crossing the bit line pairs BL0 and BL0, and BL1 and BL1. Dummy cells DC0 are provided at intersections or crossing points between the dummy word line DWL0 and the bit lines BL0 and BL1, and dummy cells DC1 are provided at intersections between the dummy word line DWL1 and the bit lines BL0 and BL1. Intermediate potentials between a power supply potential Vcc and a ground potential is held in the dummy cells DC0 and DC1.
Sense amplifiers SA0 and SA1 are connected between the bit line pairs BL and BL. The plurality of word lines WL0 and WL1, and the dummy word lines DWL0 and DWL1 are connected to a row decoder 101. The bit line pairs BL0 and BL0, and BL1 and BL1 are connected to a data input/output line pair I/O and I/O through transfer gates Q1 and Q2 comprising N channel MOS transistors. Gates of the transfer gates Q1 and Q2 are connected to a column decoder 102.
In data reading, for example, one word line WL0 is selected by the row decoder 101 so that its potential rises to the H level, whereby data in a memory cell MC connected to the word line WL0 is read out onto the bit line BL0 or BL. For example, in reading the data onto the bit line BL0, a potential of the dummy word line DWL1 is raised to the "H" level so that a potential in the dummy cell DC1 is read out onto the bit line BL0.
Therefore, a potential of the bit line BL0 will be a reference potential Vref. On the other hand, a potential of the bit line BL0 will be slightly higher or lower than the reference potential Vref. Thereafter, a potential difference between the bit line pair BL0 and BL0 is amplified by a sense amplifier SA0. Any one of the pairs of the transfer gates Q1 and Q2 is turned on by the column decoder 102, so that the data on the bit line pair BL0 and BL0 connected thereto is read out onto the data input/output line pair I/O and I/O. Now, a potential appearing on each bit line pair BL0 and BL0 in data reading will be considered.
FIG. 5 is a diagram showing a capacitance existing between the bit lines BL and BL, and a ground potential in a conventional DRAM. Referring to FIG. 5, a capacitance C1 exists between the bit lines BL and BL, and the ground potential (a fixed potential) through a substrate and a capacitance C2 exists between adjacent bit lines BL and BL. A cell capacitance of a memory cell MC connected at an intersection between a bit line BL and a word line WL is referred to Cs.
A charge stored in a memory cell MC will be CsVcc (writing of Vcc) when data of the "H" level is stored, and will be 0 (writing of 0V) when data of the "L" level is stored. In addition, a charge of CsVcc/2 (writing of Vcc/2) is stored in the dummy cells DC0 and DC1. When the bit line pairs BL and BL are to be precharged to Vcc/2 before reading operation, charges on the bit lines BL and BL will be C1Vcc/2.
In FIG. 4 described above, for example, when data is read out from a memory cell MC to the bit line BL1 and a potential from the dummy cell DC is read out onto the bit line BL1, a potential V.sub.BL1 of the bit line BL1 and a potential V.sub.BL1 of the BL1 are obtained from the following equation, respectively EQU C1Vcc/2+Cs (1/2.+-.1/2) Vcc=C1V.sub.BL1 +C2 (V.sub.BL1 -V.sub.BL0)+C2 (V.sub.BL1 -V.sub.BL1)+CsV.sub.BL1 ( 1)
(+ is for a case where the Vcc is written and - is for a case where 0 voltage is written) EQU C1Vcc/2+CsVcc/2=C1V.sub.BL1 +C2 (V.sub.BL1 -V.sub.BL2)+C2 (V.sub.BL1 -V.sub.BL1)+CsV.sub.BL1 ( 2)
wherein V.sub.BL0 is a potential of the bit line BL0 and V.sub.BL2 is a potential of the bit line BL2. In the following, it will be explained assuming that the data of the high level is read out onto the bit lines BL0, BL1 and BL2, the equation V.sub.BL0 .apprxeq.V.sub.BL1 .apprxeq.V.sub.BL2, V.sub.BL0 .apprxeq.V.sub.BL1 .apprxeq.V.sub.BL2 is given. Substituting the equation for the equation (1) and the equation (2), a potential difference .DELTA.V.sub.BL1 (=V.sub.BL1 -V.sub.BL1) between the bit lines BL1 and BL1 will be represented by the following equation (3), EQU .DELTA.V.sub.BL1 .apprxeq.CsVcc/{2 (C1+4C2+Cs)} (3)
wherein the coefficient "4" for C2 represents 2 for a capacitance generated even if adjacent bit lines have a fixed potential, 1 for a noise between paired bit lines, and 1 for a contribution of a noise received from the adjacent bit line pairs. If the distance between bit lines is reduced as a result of increased integration of memory device, the capacitance C.sub.2 between the bit lines is increased, so that a denominator of the equation (3) becomes larger. Therefore, a potential difference between the bit line pair BL and BL in reading becomes smaller due to a capacitive coupling noise between the adjacent bit lines, reducing a reading margin. As a result, sense amplifiers malfunction, thereby increasing a soft error rate.
A twisted bit line structure for reducing a capacitive coupling noise between bit lines is proposed in "A Twisted Bit Line Technique for Multi-Mb DRAMs", 1988 IEEE International Solid-State Circuits Conference, DIGEST OF TECHNICAL PAPERS, pp. 238-239, which will be described in the following.
FIG. 6 is a diagram showing a twisted bit line structure. Referring to FIG. 6, bit lines BL are divided into four, and bit lines of each of bit line pairs intersects with each other at two of the dividing points. A first pair of bit lines BL0 and BL0 intersect with each other at two dividing points which are a 1/2 point and an end point, and a second bit line pair BL1 and BL1 intersect with each other at two points which are a 1/4 point and a 3/4 point. A pattern of a basic unit is repeated with the two pairs of bit lines as a basic unit. Intersection at an end of a bit line is for overcoming an unbalance produced in capacitances and resistances between the paired bit lines.
Now, calculating a reading potential difference .DELTA.V.sub.BL1 (=.vertline.V.sub.BL1 -V.sub.BL1 .vertline.) between, for example, the bit line pair BL1 and BL1, from the following equation, EQU C1Vcc/2+(1/2.+-.1/2) CsVcc=C1V.sub.BL1 +CsV.sub.BL1 +C2 (V.sub.BL1 -V.sub.BL1)+C2/4 {(V.sub.BL1 -V.sub.BL0)+(V.sub.BL1 -V.sub.BL0)+(V.sub.BL1 -V.sub.BL2)+(V.sub.BL1 -V.sub.BL2)} ##EQU1## the following equation will be obtained, EQU V.sub.BL1 =CsVcc/{2 (C1+3C2+Cs)} (4)
and when compared with the equation (3), the coefficient for the denominator C2 is as small as 3. This is because a noise from the adjacent bit line pairs is cancelled. More specifically, it is appreciated that a reading potential difference becomes larger.
In this arrangement, however, regions are necessary in which bit lines intersect with each other at four or three points, resulting in increase of a chip area.
In addition, in the prior art shown in FIG. 4, dummy bit lines should be arranged at the opposite ends of a memory cell array to prevent an unbalance produced in a capacitance between the bit lines at ends of the memory cell array, which is described in U.S. Pat. No. 4,551,820.
In addition, usually a word line has a high resistivity and a delay difference between signals at the opposite ends of the word line is large. In order to avoid the delay difference it becomes common that in a large capacity DRAM, an interconnection having a low resistivity (for example aluminum) is arranged on a word line so that the interconnection comes into contact with the word line (lining of a word line) at several points in the array, which is described, for example, in "Mitsubishi Electric Company Technical Journal" Vol. 62, No. 7 (1988) pp 76-81. In this case, unbalance is caused also in a capacitance between a bit line pair adjacent to a lining portion. A dummy bit line is required also in this portion in order to avoid the unbalance.
As shown in FIG. 4, in a conventional dynamic semiconductor memory device, as the integration of the device and, a capacitance between adjacent bit lines are increased, there is possibilities that a reading potential difference is reduced due to a capacitive coupling noise between adjacent bit lines, so that a soft error rate is deteriorated, and a reading margin is reduced, resulting in a malfunction. In order to solve the problems, a chip area is increased, as shown in FIG. 6.